Exporting Project to SDK for AD9467/Running Example Github Code

This blog follows up the Vivado Hardware design for the AD9467 created in Vivado 2014.2. I then tried to open up the Vivado project in 2014.4, which ran fine. Before exporting to SDK in 2014.4, I had to update some of the ip-blocks in the Block Design because they were designed for 2014.2. There were 13 blocks total that needed to be upgraded. Only 7 upgraded without manual intervention.  I was unable to update the last 6 with an error telling me that the blocks could not be found in the IP Catalog. From some research,  I found that I had to add another IP Repository with the 6 "locked" blocks. Since they were not upgraded, I was unable to customize them; therefore locked.

I am still working on this problem but I wanted to export the project and program the FPGA with the software from:

http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#using_the_hdl_reference_design 

Select AD9467-FMC-EBZ Reference Design  the following menu:

You will be brought to a Github repository similar to the one found in the Hardware Design. Click the double arrow on the right-hand side of the page and download the ZIP file.  

1. Extract the files to your download directory and copy them to wherever you'd like.

2. Make sure the bitstream is written in Vivado (it should be done for you if you follow the directions in the hardware blog).

3. Export Hardware.

4. Launch SDK ensuring the workspace is the same as the one you've been saving your other projects too.

5. Create a new Empty Application

6. Import the following files to the "src" folder:
/home/zynquser/Downloads/no-OS-master/drivers/AD9467/AD9467.c
/home/zynquser/Downloads/no-OS-master/drivers/AD9467/AD9467.h
/home/zynquser/Downloads/no-OS-master/drivers/AD9517/AD9517.c
/home/zynquser/Downloads/no-OS-master/drivers/AD9517/AD9517.h
/home/zynquser/Downloads/no-OS-master/drivers/AD9517/AD9517_cfg.h
/home/zynquser/Downloads/no-OS-master/AD9467-FMC-EBZ/cf_ad9467.c
/home/zynquser/Downloads/no-OS-master/AD9467-FMC-EBZcf_ad9467.h
/home/zynquser/Downloads/no-OS-master/AD9467-FMC-EBZ/main.c
/home/zynquser/Downloads/no-OS-master/AD9467-FMC-EBZ/spi.c
/home/zynquser/Downloads/no-OS-master/AD9467-FMC-EBZ/spi.h

7. Program the FPGA - there should be no issues here

8. In order to see the output (if you check the main.c file you  will see that there are some initial tests the code runs to ensure proper connection and driver installation), open up gtkterm from the terminal.

9. Check to see which port the UART cable is connected to, usually ttyACM0. Change the permissions using sudo chmod 666 /dev/ttyACM0.

10. Run as -> Launch on Hardware (you should see the program output some print statements)

***Note: We have not connected the AD9467 to any function generator yet, this is just the instructions to load the software onto the Zedboard. Once we get the cables to connect to a function generator, we can practice with some example frequencies and take some data. Then move it to MATLAB, plot it, and see if we can get some meaningful graphs.***

Dr. McColgan's Lab Computer Setup

Workstation 1 (in the annex, shorter desk, closer to McColgan's office):

Hard Drive 1: WDC W10EZEX-75M2NA0    - CentOS 6
Hard Drive 2: ST500DM002-1BD142             - Windows (with Virtual Machine)



Workstation 2 (in the annex, taller desk, near the window):

Hard Drive 1: WDC W10EZEX-75M2NA0    - CentOS 6
Hard Drive 2: ST500DM002-1BD142             - Windows (with Virtual Machine)


During boot-up press F12  (Dell Logo Screen) and select which hard drive you plan to use.

Building/Running a Vivado Project from the Tcl Console

***Read through the whole blog before following it step by step. There are notes sprinkled throughout that are helpful to keep in mind. The blog reads as a my own personal trial and error story so some things seem superfluous when they are not! Avoid the same mistakes I made!***


Continuing on the ADC project, we ordered a board called the AD9467-FMC-250EBZ. Searching online and getting help from Joe Kujawski, I found that there is a Github repository filled with a hardware design and pre-written software that should allow us to run a program on the board seamlessly. Here is the link to the Wiki page explaining the board and it functionality:

http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#using_the_hdl_reference_design

The page above lists links to the Github repository I downloaded the zip file from. I chose the first link (Zed HDL Reference Design) from this download section to navigate to the hardware design:

Once at the new page I simply click the double arrow on the right hand side of the page (<>) to get a new menu which appears directly underneath it:

Before:

After clicking <>:

Notice in the picture above there is an option for "Download Zip". Click this and the download will start automatically. Once downloaded, navigate to your Downloads directory and extract the files to whichever location you choose. I typically go with the strategy of extracting right in the Downloads directory and copying the file to a new one ("Vivado Projects" perhaps) later on. But if I forget where I copy it to I know it is always in the Download folder!

Once extracted I followed the directions from a great tutorial found here:

http://wiki.analog.com/resources/fpga/docs/hdl#building_hdl


Starting with "Building with Vivado," follow the instructions for building the libraries for your project and generating your block design for the project (all done through the Tcl console).

***Note: The project files downloaded from the Github repository are only compatible with Vivado 2014.2. The Virtual Machine I am working on did not have this Xilinx version installed so it is important to check before going ahead with the instructions. Completing the instructions from the tutorial page using Vivado 2014.2 will result in an error from the Tcl console that reads:

ERROR: This project requires Vivado 2014.2.

    while executing

"adi_project_create $project_name"

    (file "./system_project.tcl" line 7)

***Additional Notes: Running the Tcl script for building the libraries loads just fine in 2014.2, but trying to run the project files (generate block diagram) comes up with this error:

ERROR: [BD 5-216] VLNV <analog.com:user:util_i2c_mixer:1.0> is not supported for this version of the tools.

ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing

"create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer"

    invoked from within

"set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]"

    (file "../../../projects/common/zed/zed_system_bd.tcl" line 66)

    while executing

"source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl"

    (file "system_bd.tcl" line 2)

    while executing

"source system_bd.tcl"

    (procedure "adi_project_create" line 107)

    invoked from within

"adi_project_create $project_name"

    (file "./system_project.tcl" line 7)

Solving this problem takes awhile whether or not you know what you are doing. It is important to RUN EVERY SINGLE TCL SCRIPT FOUND IN THIS DIRECTORY:

/home/zynquser/Downloads/hdl-master/library

There are roughly 40 .tcl files (Tcl scripts) that need to be run before getting to the next step of the process; loading the project file you need.

Recapping:

1. Download

• ZED HDL Reference Design: https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9467_fmc/zed

2. Extract into Downloads folder.

3. Open Vivado 2014.2

4. Build every sub-library listed in:

          /home/zynquser/Downloads/hdl-master/library

         ***This requires entering these instructions for ALL 42 items in the library folder:***

        

Library

We need to build the libraries first. So open the GUI and at the TCL console change the directory to where the libraries are. You must build ALL the libraries (each folder insider the library directory).

cd /home/zynquser/Downloads/hdl-master/library/axi_ad6676

You should see a tcl script axi_ad6676_ip.tcl in this directory. We just need to run that script.

source ./axi_ad9122_ip.tcl

You will see commands being executed, and the GUI will change into a project window. There is nothing to do here, you could browse the source, if you prefer to do synthesis as stand alone and such things. If you are not fancy about it, just quit and continue to build libraries for other cores.

5. Load the project you need: It will be AD9467 for this specific application:

Projects

After building all the libraries (or the ones you are interested in), you can run the project (generate bitstream and export the design to SDK). This is the same procedure as above except for changes in path and tcl file names.

Let's open the GUI again and at the TCL console change the directory to where the project is.

cd //home/zynquser/Downloads/hdl-master/projects/ad9467_fmc/zed

You should see a tcl script system_project.tcl in this directory. We just need to run that script.

source ./system_project.tcl

You will see commands being executed, and the GUI will change into a project window. The script will create a board design in IPI, generate all the IP targets, synthesize the netlist and implementation. It also exports the hardware to SDK.

6. The Tcl script we just ran will take care of everything we usually do with Vivado: Run Synthesis, Run Implementation, Write Bitsream, Export Hardware. In addition the pin assignments for the FMC-LPC portion of the Zedoboard is automated by the Tcl script so no need to go in to I/O Ports and assign specific Sites. The only thing left to do is Launch SDK with your project.

***Although it is somewhat obvious, this is how the AD9467 connects to the Zedboard:***

 It is officially time to Launch SDK and begin loading software onto the Zedboard (Program FPGA). Luckily, there is another Github repository that has pre-written software. I will explain those steps in the next blog post.

General Info PART 2 - AD9467 - FMC -250EBZ

The AD9467 uses standard Serial Port Interfacing (SPI)

SPI is a synchronous data bus meaning that it uses separate lines for data and a "clock" that keeps both sides in perfect sync. The "clock," as we familiarized ourselves with using the Maxim 11205 ADC, is an oscillating signal that tells the receiver exactly when to sample the bits on the data line. Sometimes the receiver will sample the bits from the data line when the clock goes from HI to LO or when it goes from LO to HI.

Looking at the datasheet for the AD9467, I found that the board comes equipped with three Serial Port Pins: SCLK, SDIO, and CSB.

The falling edge of the CSB, along with the rising edge of the SCLK, determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. Here is an example of a timing diagram for the board:

As you can see in the diagram, when the CSB line is brought low, the device processes SDIO and SCLK instructions. After the 16-bit instruction set, the CSB goes high, thus ending communication with the other two pins. 

Data can be sent in either MSB (most significant bit) or LSB (least significant) mode. In MSB first mode, the data is transmitted starting with the 16th bit in descending order towards the 1st bit. The opposite is true for LSB first mode. 

Here is a good link regarding interfacing high speed ADCs via SPI:

http://www.analog.com/media/en/technical-documentation/application-notes/56755538964965031881813AN_877.pdf

Additional Notes from Joe:

At a high level, RS232 is single ended and uses a wide voltage swing (the standard actually calls for +/-12V). This has a problem of being pretty high power and being very limited in terms of speed of transmission.  RS232 is susceptible to noise and differences in the sending and receiving ground voltages, so the longer the distance between the source and destination, the more likely it is that there is an error.

LVDS is a current drive system (instead of Voltage drive) which means that it does not care about any differences in the ground potential at the source vs. the destination.  Also, since it is differential, noise will be 'picked up' on both lines at the same time and will be cancelled out.  Finally, LVDS is very high speed compared to RS232 mainly due to the many advantages I already listed.

http://www.eetimes.com/document.asp?doc_id=1272339

General Info - AD9467 - FMC -250EBZ

The AD9467 is a 16 - bit monolithic, IF sampling analog-to-digital converter (ADC). The board shipped to us has two good data sheets:

Datasheet - http://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf

Board Evaluation Guide - http://www.analog.com/media/en/technical-documentation/evaluation-documentation/UG-200.pdf

Back up two steps and define some important terms from the first sentence:

1) monolithic IC- A monolithic integrated circuit, in general, is a type of IC that is made on the surface of a single crystal semiconductor like a silicon wafer. A process called "planar technology must be used in the single block (monolith) and be interconnected to the insulating layer over the same body of the semiconductor to produce a solid integral monolithic IC.

2) Integrator - integrated based ADC. The input voltage is integrated, compared to a reference voltage, and converted into a digital representation. The integrator uses a reference capacitor which is chosen depending on the bandwidth of the signal. Wikipedia has a good link in its op-amp section explaining an inverting integrator. Replace the resistor connecting the positive input to the output of a differential amplifier and get an inverting amplifier.

3) IF - intermediate frequency sampling - essentially taking an input signal and mixing it with a signal produced by a local oscillator to get what is called a beat or difference frequency. From what I understand the signals are added/subtracted using the principle of superposition and the resulting frequency is more "powerful" in that it is more easily manipulated/amplified/analyzed for a specific application.

3) Wide bandwidth/bandwidth - the difference in the upper and lower frequencies in a set of frequencies. In the radio world, radio companies will purchase a given bandwidth that says they have the right to broadcast over a slice of frequency in the sound spectrum of the geographic location they are located in.

4) NOTES FROM DATASHEET*****"The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Figure 1. A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range."****

 - low voltage differential input clock or the board uses low voltage differential signaling (LVDS) a physical layer characterization describing electrical components that can run aat very low power yet very high speeds - often in combination with twisted pair coaxial cable inputs that reduce electromagnetic interference from other sources.

-DCO - Data Clock Output -

- SPI - Serial Port Interfacing -

Angle Encoder Revisited

I had a couple ideas I wanted to get out onto paper before I forget them regarding the errors that arise with the angle encoder. For the first version of the hardware, with the first two pins of the PMODs being used as a single interrupt, the threshold for which the pin changes from a HI to LO State is unclear. As the encoder shaft spins, the value on one of the pins will shift from 1 to 0 seemingly if there is any voltage above 0.0 V. But this surely cannot be the case. I have tested the chip/Zedboard combination to find where this threshold exists using a voltmeter but have come up empty on my attempts. I hold that the value is changing too quickly for the voltmeter to pickup the incremental changes sent to the Zedboard from the encoder. I know that the value is changing rapidly because I print out the value from "encoded" which is the combination from both encoder pins which should read a 11 10 01 or 00. Moving clockwise should follow the same order over and over and the same follows for counter-clockwise. There must be some noise, instead that is mucking up the cycle causing the algorithm I have written to break down. If I can find this threshold in the PMOD for where the change exists, I should have a properly working angle encoder.