General AXI Properties/About AXI (unfinished)

AXI
-AXI is a type of bus that connects modules on a chip
-two types: Slaves and Masters

AXI Masters
-initiate transactions between modules (transactions can be seen as read/write data being sent back and forth)

AXI Slaves
-respond to initiated transactions made by Masters
-addresses for slave modules can be defined by the user but no two slaves can have any address overlap

AXI Interconnect
-capable of a lot of actions
-connect master and slave modules
-can be hierarchical
-one AXI Interconnect can have up 16 slaves and 16 masters
-can convert 64 bit transactions to 32 bit transactions if needed





AXI Addressing
-Masters send read/write commands through the AXI Interconnect to slaves
-slaves have address ranges that commands from masters must fall into
Examples: UART: 0x40000000-0x40000FFF
                   GPIO: 0x40001000-0x40001FFF
                   RAM: 0x40010000-0x4001FFFF







**The AXI interconnect is a vital piece when assembling a block design in Xilinx Vivado.**