Key Terms Notes -- Chapter 2 (Zynq Book)

• Application Processing Unit (APU)
• comprised of two ARM processing cores (each with associated computational units: a NEON Media Processing Engine (MPE) and Floating Point Unit (FPU))
• ARM can operate at up to 1 GHz
• Each core contains separate Level 1 caches
• One for data, one for instructions
• Both are 32 KB
• permits local storage of frequently required data and instructions for fast access times and optimal processor performance
• Both ARM cores SHARE a larger 512 KB Level 2 cache for instructions and data
• Snoop Control Unit (SCU)
• undertakes several tasks relating to interfacing between the processors and the Level 1 and Level 2 cache memories 
• snooping is one of several mechanisms for ensuring cache coherency or managing the consistency of data across shared cache resources
• A cache is place to temporarily store information in a computing environment; thus speeding up access times