Recreating the sum_io

The first step is to launch vivado HLS (2016).

* Helpful Blog Post For Review: Things We Should All Know About Vivado HLS

Create a new project > name the project > Choose a location > Next

Add Files: Here you want to add the file sum_io.c you may need to download this from Mike's files if it is not already saved.
Top Function: sum_io > Next

Add Testbench Files > sum_io.test.c > Next

Solution Configuration:
Solution Name > Solution1
Part Selection > Zedboard > Finish

Project Tab > Run C Simulation

Under Source > Select sum_io.c > Directives Tab > Right Click sum_io > Insert Directive >  Interface > ap_ctrl_none

Run C Simulation

Solution > Run C Synthesis

Solution > Export RTL > Options:VHDL > OK

Now you are ready to launch Vivado (2016)

*Helpful Blog Post Fore Review: Things We Should All Know Vivado

New Project > name the project  > Choose Location > Next

Choose Zedboard Rev C > Next > Finish

Create New Block Design > Name it

Right Click > Add IP > ZYNQ7 Processing System > Run Block Automation

Now we need to add seven GPIOs:

Rt. Click > add IP > AXI GPIO > Run Connection Automation > ✓GPIO > LEDs > Run Connection Automation

Next, insert 3 AXI GPIOs, an Adder/Subtracter and a Constant.

Double click one GPIO1 > IP Configuration > ✓All Outputs > GPIO Width 15 > GPIO Width 32 >
ok

Double click one GPIO2 > IP Configuration > ✓All Outputs > GPIO Width 15 > GPIO Width 32 > ok
Double click one GPIO3 > IP Configuration > ✓All Inputs > GPIO Width 16 > GPIO Width 32 > ok
Double click one AddSub > Basic Tab > Input Width 15 > Output Width 16 > ok

Connect the output of gpio1 to the first input (A) on the add/Sub  and connect the output from gpio2 to the second input (B) on the add/sub. Next connect the output of the adder/sub to the input of gpio3. Finally connect the constant to the bottom input of the add/sub (CE). Now Run Connection Automation. Your block diagram should look like the bottom right corner of the picture below.

Next add three more AXI GPIOs.

Double click one GPIO4 > IP Configuration > ✓All Outputs > GPIO Width 16 > GPIO Width 32 > ok
Double click one GPIO5 > IP Configuration > ✓All Outputs > GPIO Width 16 > GPIO Width 32 > ok
Double click one GPIO6 > IP Configuration > ✓All Inputs > GPIO Width 32 > GPIO Width 32 > ok

Now we need to insert the HLS Repository that we made in the first step.

Project Settings > IP (on left) > Repository Manager > + > Select the path where you saved your HLS file (Ex. Sams_FPGA_projects/Sam_Sum_io/soln1/impl/ip) > Apply  > ok

Right Click > Add IP > sum_io

Now you want to connect the output of gpio4 to the top input of the sum_io and the output of gpio5 to the bottom input. Next connect the output of the sum_io to gpio6.
Run Connection Automation and your block design should be complete.

Now you can save and validate your design. 

Tools > Validate Design

Switch to the sources tab by selecting window > sources. Right click on the top level system > Create HDL Wrapper

Flow Navigator > Generate Bitstream > Open Implemented Design > ok

File > Export > Export Hardware > ✓ Include Bitstream 

File > Launch SDK > ok

Create a new empty application

Expand sumIO > Right Click on src > import > AddComp.c

Now you can program the FPGA. Once the FPGA board is programed

Right click on sumIO > Run As > Launch On Hardware

NOTE: I found that it was useful to run the code using GTKterm. I was unable to get it to work anywhere else.

Your code takes two values and adds them together. The sums are what should be printed out in the terminal. You should get one that says Xilinz Output Adder = 2 and HLS Output Adder = 4. You can change these output values by changing the input values in the code.