***Read through the whole blog before following it step by step. There are notes sprinkled throughout that are helpful to keep in mind. The blog reads as a my own personal trial and error story so some things seem superfluous when they are not! Avoid the same mistakes I made!***
Continuing on the ADC project, we ordered a board called the AD9467-FMC-250EBZ. Searching online and getting help from Joe Kujawski, I found that there is a Github repository filled with a hardware design and pre-written software that
should allow us to run a program on the board seamlessly. Here is the link to the Wiki page explaining the board and it functionality:
http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#using_the_hdl_reference_design
The page above lists links to the Github repository I downloaded the zip file from. I chose the first link (Zed HDL Reference Design) from this download section to navigate to the hardware design:
Once at the new page I simply click the double arrow on the right hand side of the page (<>) to get a new menu which appears directly underneath it:
Before:
After clicking <>:
Notice in the picture above there is an option for "Download Zip". Click this and the download will start automatically. Once downloaded, navigate to your Downloads directory and extract the files to whichever location you choose. I typically go with the strategy of extracting right in the Downloads directory and copying the file to a new one ("Vivado Projects" perhaps) later on. But if I forget where I copy it to I know it is always in the Download folder!
Once extracted I followed the directions from a great tutorial found here:
http://wiki.analog.com/resources/fpga/docs/hdl#building_hdl
Starting with "Building with Vivado," follow the instructions for building the libraries for your project and generating your block design for the project (all done through the Tcl console).
***Note: The project files downloaded from the Github repository are only compatible with Vivado 2014.2. The Virtual Machine I am working on did not have this Xilinx version installed so it is important to check before going ahead with the instructions. Completing the instructions from the tutorial page using Vivado 2014.2 will result in an error from the Tcl console that reads:
ERROR: This project requires Vivado 2014.2.
while executing
"adi_project_create $project_name"
(file "./system_project.tcl" line 7)
***Additional Notes: Running the Tcl script for building the libraries loads just fine in 2014.2, but trying to run the project files (generate block diagram) comes up with this error:
ERROR: [BD 5-216] VLNV <analog.com:user:util_i2c_mixer:1.0> is not supported for this version of the tools.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer"
invoked from within
"set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]"
(file "../../../projects/common/zed/zed_system_bd.tcl" line 66)
while executing
"source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl"
(file "system_bd.tcl" line 2)
while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 107)
invoked from within
"adi_project_create $project_name"
(file "./system_project.tcl" line 7)
Solving this problem takes awhile whether or not you know what you are doing. It is important to RUN EVERY SINGLE TCL SCRIPT FOUND IN THIS DIRECTORY:
/home/zynquser/Downloads/hdl-master/library
There are roughly 40 .tcl files (Tcl scripts) that need to be run before getting to the next step of the process; loading the project file you need.
Recapping:
1. Download
2. Extract into Downloads folder.
3. Open Vivado 2014.2
4. Build every sub-library listed in:
/home/zynquser/Downloads/hdl-master/library
***This requires entering these instructions for ALL 42 items in the library folder:***
Library
We need to build the libraries first. So open the
GUI and at the TCL console change the directory to where the libraries are. You must build
ALL the libraries (each folder insider the library directory).
cd /home/zynquser/Downloads/hdl-master/library/axi_ad6676
You should see a tcl script axi_ad6676_ip.tcl in this directory. We just need to run that script.
source ./axi_ad9122_ip.tcl
You will see commands being executed, and the
GUI will change into a project window. There is nothing to do here, you could browse the source, if you prefer to do synthesis as stand alone and such things. If you are not fancy about it, just quit and continue to build libraries for other cores.
5. Load the project you need: It will be AD9467 for this specific application:
Projects
After building all the libraries (or the ones you are interested in), you can run the project (generate bitstream and export the design to SDK). This is the same procedure as above except for changes in path and tcl file names.
Let's open the
GUI again and at the TCL console change the directory to where the project is.
cd //home/zynquser/Downloads/hdl-master/projects/ad9467_fmc/zed
You should see a tcl script system_project.tcl in this directory. We just need to run that script.
source ./system_project.tcl
You will see commands being executed, and the
GUI will change into a project window. The script will create a board design in IPI, generate all the IP targets, synthesize the netlist and implementation. It also exports the hardware to SDK.
6. The Tcl script we just ran will take care of everything we usually do with Vivado: Run Synthesis, Run Implementation, Write Bitsream, Export Hardware. In addition the pin assignments for the FMC-LPC portion of the Zedoboard is automated by the Tcl script so no need to go in to I/O Ports and assign specific Sites. The only thing left to do is Launch SDK with your project.
***Although it is somewhat obvious, this is how the AD9467 connects to the Zedboard:***
It is officially time to Launch SDK and begin loading software onto the Zedboard (Program FPGA). Luckily, there is another Github repository that has pre-written software. I will explain those steps in the next blog post.
