Things We Should All Know (Vivado HLS)

The Xilinx tool-chain, as it pertains to running Petalinux on the Zedboard is as follows:

Vivado HLS --> Vivado  --> Petalinux --> SDCard (Boot on Board).

To fully  understand what is happening at each of these stages I will go through it step by step.

A) Developing IP in Vivado High-Level Synthesis

Vivado HLS is a tool used to accelerate IP creation by enabling C/C++/SystemC programs (in our case I translated the first part of the PSD Python algorithm called Pre-Filter from Python to C, so it could be used in HLS and run on the Zedboard) to be directly targeted into Xilinx Programmable devices (Zedboard) without the need to manually create RTL.

Steps

• Open Vivado HLS (on the command line, any directory, type: vivado_hls)
• Create New Project --> Pre_Filter.prj --> Next
• Add Source Files --> Pre_Filter.c (can be found on another blog, but great to write your own) --> Next
• Top Function can be selected from browse (called Pre)
• The top function is the function that will be synthesized
• Add TestBench Files --> Pre_Filter.c --> Next
• Our test bench will be the same as our source file
• Choose Zedboard in Part Selection --> Finish
• Solution Name: High-Level Synthesis provides the initial default name solution1 but any name can be specified for the solution. 
• Clock: The clock period is specified using units of ns. The clock period used for synthesis is the clock period minus the clock uncertainty. High-Level Synthesis uses the timing information in the technology library to create the RTL design. The clock uncertainty value allows a user controllable margin to account for any increases in net delays due to RTL synthesis, place and route. If not specified in ns, the clock uncertainty defaults to 12.5% of the clock period.
• Run C-Simulation (Project Tab --> Run C - Simulation)
• Ensure no errors occur during compiling, you would not want to get through the block design without a working code. This would most likely be found during synthesis anyhow, but its good practice to run the simulation as a check. 
• Insert Directive in Top Function

• On the right side of the screen, there are two tabs, Outline and Directive. On the Explorer, under Source, be sure to select your Pre_Filter.c file and load it into the main window. Then select Directive on the right side of the screen.
• Right-click on Pre and insert directive, choosing interface and changing the mode to s_axilite
  
• Run C-Synthesis (Project Tab --> Run C - Synthesis)
• Solution Tab --> Export RTL --> OK
• Select IP Catalog and VHDL

You are now ready to import your newly created IP into Vivado and complete your block design! (See next blog)