Things We Should All Know (Vivado)

The Xilinx tool-chain, as it pertains to running Petalinux on the Zedboard is as follows:

Vivado HLS --> Vivado  --> Petalinux --> SDCard (Boot on Board).

To fully  understand what is happening at each of these stages I will go through it step by step.

B) Creating a Block Design in Vivado Design Suite

Vivado HLS automates  the construction of an IP core (block) that can be inserted into a hardware design (block diagram) to be eventually integrated with Petalinux.

Steps

• Open Vivado (on the command line, any directory, type: vivado)
• Create a new Project --> Pre_Filter as the name
• Follow the instructions from the Zynq Book Tutorial (part 1 to complete the initialization instructions including adding the processing system to your block design, link to download tutorials below, First Designs in Zynq is the header for where you should start)
• http://www.zynqbook.com/download-tuts.html
• Add 3 AXI GPIO Blocks, one for the LEDs, one for the push buttons, and one for the DIPs switches, and run connection automation
• Add HLS repository --> Choose Project Settings under Project Manager in Flow Navigator
• Choose IP on the left pane and click the "plus" icon to add a fresh IP repo
  
• The repository you want to add is in the HLS directory:
•  <you choose initial path>/Pre_Filter.prj/solution1/impl/ip
• Click Apply and OK
• In your block design window, select Add IP again. This time type "Pre" (or whatever your top function name was in HLS) and select the block that comes from the repository. It will look like this when it is added:

• Click on the processing system block in your design to open up Re-customize IP:
  

• Select IRQ_F2P[15:0] from PL-PS Interrupt Ports. Fabric Interrupts will need to be checked also (see above picture)
• Connect the interrupt port from the HLS IP block to the  IRQ_F2P[0:0] port of the processing system:

• Click Regenerate Layout, and your block design should look close to this: 

• Click Validate Design to ensure no design errors
• Create HDL wrapper inside the sources tab --> right -click yellow pyramid file, Create HDL wrapper:
  
• In the Flow Navigator, click Generate Bitstream. This command Runs Synthesis, Runs Implementation, and Generates the Bitstream (describing the programmable logic)
• This task will take a while, don't fret
• Click File --> Export Hardware
• Click File --> Launch SDK to update the old hardware design

You have now created a block design that uses a custom IP with interrupt connected to a Zynq processing system. The next step is to integrate the hardware description file (just created in Vivado) into Petalinux so that every module created in Vivado, whether its our module, the LEDs, the buttons, or the switches can be accessed on the Zedboard.

(see next blog)