Pre-Filter C Program (without CSV File read) Needed for Vivado HLS

#include <stdio.h>

int main(){
Pre();

}

int Pre(){


/*Pre-Filter*/
double time[502] = {-2.7e-07,-2.68e-07,-2.66e-07,-2.64e-07,-2.62e-07,-2.6e-07,-2.58e-07,-2.56e-07,-2.54e-07,-2.52e-07,-2.5e-07,-2.48e-07,-2.46e-07,-2.44e-07,-2.42e-07,-2.4e-07,-2.38e-07,-2.36e-07,-2.34e-07,-2.32e-07,-2.3e-07,-2.28e-07,-2.26e-07,-2.24e-07,-2.22e-07,-2.2e-07,-2.18e-07,-2.16e-07,-2.14e-07,-2.12e-07,-2.1e-07,-2.08e-07,-2.06e-07,-2.04e-07,-2.02e-07,-2e-07,-1.98e-07,-1.96e-07,-1.94e-07,-1.92e-07,-1.9e-07,-1.88e-07,-1.86e-07,-1.84e-07,-1.82e-07,-1.8e-07,-1.78e-07,-1.76e-07,-1.74e-07,-1.72e-07,-1.7e-07,-1.68e-07,-1.66e-07,-1.64e-07,-1.62e-07,-1.6e-07,-1.58e-07,-1.56e-07,-1.54e-07,-1.52e-07,-1.5e-07,-1.48e-07,-1.46e-07,-1.44e-07,-1.42e-07,-1.4e-07,-1.38e-07,-1.36e-07,-1.34e-07,-1.32e-07,-1.3e-07,-1.28e-07,-1.26e-07,-1.24e-07,-1.22e-07,-1.2e-07,-1.18e-07,-1.16e-07,-1.14e-07,-1.12e-07,-1.1e-07,-1.08e-07,-1.06e-07,-1.04e-07,-1.02e-07,-1e-07,-9.84e-08,-9.64e-08,-9.44e-08,-9.24e-08,-9.04e-08,-8.84e-08,-8.64e-08,-8.44e-08,-8.24e-08,-8.04e-08,-7.84e-08,-7.64e-08,-7.44e-08,-7.24e-08,-7.04e-08,-6.84e-08,-6.64e-08,-6.44e-08,-6.24e-08,-6.04e-08,-5.84e-08,-5.64e-08,-5.44e-08,-5.24e-08,-5.04e-08,-4.84e-08,-4.64e-08,-4.44e-08,-4.24e-08,-4.04e-08,-3.84e-08,-3.64e-08,-3.44e-08,-3.24e-08,-3.04e-08,-2.84e-08,-2.64e-08,-2.44e-08,-2.24e-08,-2.04e-08,-1.84e-08,-1.64e-08,-1.44e-08,-1.24e-08,-1.04e-08,-8.37e-09,-6.37e-09,-4.37e-09,-2.37e-09,-3.69e-10,1.63e-09,3.63e-09,5.63e-09,7.63e-09,9.63e-09,1.16e-08,1.36e-08,1.56e-08,1.76e-08,1.96e-08,2.16e-08,2.36e-08,2.56e-08,2.76e-08,2.96e-08,3.16e-08,3.36e-08,3.56e-08,3.76e-08,3.96e-08,4.16e-08,4.36e-08,4.56e-08,4.76e-08,4.96e-08,5.16e-08,5.36e-08,5.56e-08,5.76e-08,5.96e-08,6.16e-08,6.36e-08,6.56e-08,6.76e-08,6.96e-08,7.16e-08,7.36e-08,7.56e-08,7.76e-08,7.96e-08,8.16e-08,8.36e-08,8.56e-08,8.76e-08,8.96e-08,9.16e-08,9.36e-08,9.56e-08,9.76e-08,9.96e-08,1.02e-07,1.04e-07,1.06e-07,1.08e-07,1.1e-07,1.12e-07,1.14e-07,1.16e-07,1.18e-07,1.2e-07,1.22e-07,1.24e-07,1.26e-07,1.28e-07,1.3e-07,1.32e-07,1.34e-07,1.36e-07,1.38e-07,1.4e-07,1.42e-07,1.44e-07,1.46e-07,1.48e-07,1.5e-07,1.52e-07,1.54e-07,1.56e-07,1.58e-07,1.6e-07,1.62e-07,1.64e-07,1.66e-07,1.68e-07,1.7e-07,1.72e-07,1.74e-07,1.76e-07,1.78e-07,1.8e-07,1.82e-07,1.84e-07,1.86e-07,1.88e-07,1.9e-07,1.92e-07,1.94e-07,1.96e-07,1.98e-07,2e-07,2.02e-07,2.04e-07,2.06e-07,2.08e-07,2.1e-07,2.12e-07,2.14e-07,2.16e-07,2.18e-07,2.2e-07,2.22e-07,2.24e-07,2.26e-07,2.28e-07,2.3e-07,2.32e-07,2.34e-07,2.36e-07,2.38e-07,2.4e-07,2.42e-07,2.44e-07,2.46e-07,2.48e-07,2.5e-07,2.52e-07,2.54e-07,2.56e-07,2.58e-07,2.6e-07,2.62e-07,2.64e-07,2.66e-07,2.68e-07,2.7e-07,2.72e-07,2.74e-07,2.76e-07,2.78e-07,2.8e-07,2.82e-07,2.84e-07,2.86e-07,2.88e-07,2.9e-07,2.92e-07,2.94e-07,2.96e-07,2.98e-07,3e-07,3.02e-07,3.04e-07,3.06e-07,3.08e-07,3.1e-07,3.12e-07,3.14e-07,3.16e-07,3.18e-07,3.2e-07,3.22e-07,3.24e-07,3.26e-07,3.28e-07,3.3e-07,3.32e-07,3.34e-07,3.36e-07,3.38e-07,3.4e-07,3.42e-07,3.44e-07,3.46e-07,3.48e-07,3.5e-07,3.52e-07,3.54e-07,3.56e-07,3.58e-07,3.6e-07,3.62e-07,3.64e-07,3.66e-07,3.68e-07,3.7e-07,3.72e-07,3.74e-07,3.76e-07,3.78e-07,3.8e-07,3.82e-07,3.84e-07,3.86e-07,3.88e-07,3.9e-07,3.92e-07,3.94e-07,3.96e-07,3.98e-07,4e-07,4.02e-07,4.04e-07,4.06e-07,4.08e-07,4.1e-07,4.12e-07,4.14e-07,4.16e-07,4.18e-07,4.2e-07,4.22e-07,4.24e-07,4.26e-07,4.28e-07,4.3e-07,4.32e-07,4.34e-07,4.36e-07,4.38e-07,4.4e-07,4.42e-07,4.44e-07,4.46e-07,4.48e-07,4.5e-07,4.52e-07,4.54e-07,4.56e-07,4.58e-07,4.6e-07,4.62e-07,4.64e-07,4.66e-07,4.68e-07,4.7e-07,4.72e-07,4.74e-07,4.76e-07,4.78e-07,4.8e-07,4.82e-07,4.84e-07,4.86e-07,4.88e-07,4.9e-07,4.92e-07,4.94e-07,4.96e-07,4.98e-07,5e-07,5.02e-07,5.04e-07,5.06e-07,5.08e-07,5.1e-07,5.12e-07,5.14e-07,5.16e-07,5.18e-07,5.2e-07,5.22e-07,5.24e-07,5.26e-07,5.28e-07,5.3e-07,5.32e-07,5.34e-07,5.36e-07,5.38e-07,5.4e-07,5.42e-07,5.44e-07,5.46e-07,5.48e-07,5.5e-07,5.52e-07,5.54e-07,5.56e-07,5.58e-07,5.6e-07,5.62e-07,5.64e-07,5.66e-07,5.68e-07,5.7e-07,5.72e-07,5.74e-07,5.76e-07,5.78e-07,5.8e-07,5.82e-07,5.84e-07,5.86e-07,5.88e-07,5.9e-07,5.92e-07,5.94e-07,5.96e-07,5.98e-07,6e-07,6.02e-07,6.04e-07,6.06e-07,6.08e-07,6.1e-07,6.12e-07,6.14e-07,6.16e-07,6.18e-07,6.2e-07,6.22e-07,6.24e-07,6.26e-07,6.28e-07,6.3e-07,6.32e-07,6.34e-07,6.36e-07,6.38e-07,6.4e-07,6.42e-07,6.44e-07,6.46e-07,6.48e-07,6.5e-07,6.52e-07,6.54e-07,6.56e-07,6.58e-07,6.6e-07,6.62e-07,6.64e-07,6.66e-07,6.68e-07,6.7e-07,6.72e-07,6.74e-07,6.76e-07,6.78e-07,6.8e-07,6.82e-07,6.84e-07,6.86e-07,6.88e-07,6.9e-07,6.92e-07,6.94e-07,6.96e-07,6.98e-07,7e-07,7.02e-07,7.04e-07,7.06e-07,7.08e-07,7.1e-07,7.12e-07,7.14e-07,7.16e-07,7.18e-07,7.2e-07,7.22e-07,7.24e-07,7.26e-07,7.28e-07,7.3e-07,7.32e-07
};
double amp[502] = {-0.00650676,-0.00330688,-0.00650676,-0.00330688,-0.00490682,-0.00330688,-0.00490682,-0.00490682,-0.00330688,-0.00330688,-0.00650676,-0.00490682,-0.00330688,-0.00330688,-0.00330688,-0.00650676,-0.00170694,-0.00330688,-0.00490682,-0.00490682,-0.00170694,-0.00490682,-0.00650676,-0.00650676,-0.00490682,-0.000107004,-0.00170694,-0.00330688,-0.00650676,-0.00490682,-0.00170694,-0.00330688,-0.00650676,-0.00170694,-0.00170694,-0.00170694,-0.00330688,-0.00330688,-0.00330688,-0.00490682,-0.00490682,-0.00490682,-0.00490682,-0.00170694,-0.00490682,-0.00650676,-0.00490682,-0.00330688,-0.00650676,-0.000107004,-0.000107004,-0.00650676,-0.00330688,-0.00330688,-0.0081067,-0.00650676,-0.00490682,-0.00490682,-0.00330688,-0.00170694,-0.00650676,-0.000107004,-0.00650676,-0.0081067,-0.00650676,-0.00490682,-0.00650676,-0.00490682,-0.00490682,-0.00330688,-0.00490682,-0.00650676,-0.00650676,-0.0081067,-0.00490682,-0.00490682,-0.00490682,-0.00330688,-0.00330688,-0.00650676,-0.0081067,-0.00650676,-0.00490682,-0.00330688,-0.000107004,-0.00330688,-0.00490682,0.00149293,-0.00490682,-0.00330688,-0.00650676,-0.000107004,-0.00330688,-0.00650676,-0.00170694,-0.00490682,-0.00330688,-0.00330688,-0.00330688,-0.00490682,-0.00330688,-0.00490682,-0.00330688,-0.00330688,-0.00650676,-0.00650676,-0.00330688,-0.00330688,-0.00330688,-0.00170694,-0.000107004,-0.00330688,-0.00650676,-0.00490682,-0.00490682,-0.00490682,-0.000107004,-0.00170694,-0.00490682,-0.00490682,-0.0081067,-0.00650676,-0.00650676,-0.0129065,-0.00970664,-0.0129065,-0.0161064,-0.0177063,-0.0193063,-0.0225061,-0.025706,-0.0321058,-0.025706,-0.0337057,-0.0337057,-0.0369056,-0.0353057,-0.0385055,-0.0385055,-0.0433053,-0.0433053,-0.0465052,-0.0481052,-0.051305,-0.051305,-0.0545049,-0.051305,-0.052905,-0.0561049,-0.0545049,-0.0545049,-0.0609047,-0.0609047,-0.0545049,-0.0593047,-0.0593047,-0.0593047,-0.0609047,-0.0577048,-0.0561049,-0.0657045,-0.0561049,-0.0609047,-0.0609047,-0.0609047,-0.0609047,-0.0625046,-0.0609047,-0.0609047,-0.0641045,-0.0577048,-0.0609047,-0.0609047,-0.0609047,-0.0609047,-0.0625046,-0.0577048,-0.0609047,-0.0625046,-0.0593047,-0.0561049,-0.0577048,-0.0561049,-0.051305,-0.0577048,-0.0545049,-0.0577048,-0.0593047,-0.0577048,-0.0545049,-0.052905,-0.051305,-0.0593047,-0.0481052,-0.052905,-0.0497051,-0.052905,-0.051305,-0.0481052,-0.0497051,-0.0481052,-0.0481052,-0.0497051,-0.0433053,-0.0417054,-0.0465052,-0.0449053,-0.0417054,-0.0417054,-0.0417054,-0.0385055,-0.0417054,-0.0433053,-0.0385055,-0.0401055,-0.0353057,-0.0385055,-0.0433053,-0.0401055,-0.0337057,-0.0337057,-0.027306,-0.0337057,-0.0337057,-0.0289059,-0.0305058,-0.0321058,-0.0305058,-0.0289059,-0.027306,-0.027306,-0.025706,-0.0289059,-0.027306,-0.0289059,-0.0241061,-0.0209062,-0.025706,-0.0241061,-0.0241061,-0.027306,-0.0225061,-0.0241061,-0.0225061,-0.0209062,-0.0209062,-0.0209062,-0.0225061,-0.0209062,-0.0193063,-0.0177063,-0.0177063,-0.0177063,-0.0177063,-0.0209062,-0.0161064,-0.0177063,-0.0161064,-0.0177063,-0.0161064,-0.0161064,-0.0177063,-0.0145065,-0.0129065,-0.0161064,-0.0129065,-0.0113066,-0.0113066,-0.0129065,-0.0113066,-0.0129065,-0.0129065,-0.0129065,-0.0113066,-0.0129065,-0.0081067,-0.0129065,-0.0113066,-0.0081067,-0.0129065,-0.0113066,-0.0113066,-0.0113066,-0.0113066,-0.00970664,-0.0113066,-0.0081067,-0.0081067,-0.0113066,-0.0081067,-0.00650676,-0.0081067,-0.00970664,-0.0081067,-0.00650676,-0.00650676,-0.0081067,-0.0081067,-0.0081067,-0.0081067,-0.00970664,-0.00650676,-0.00330688,-0.00970664,-0.00490682,-0.00490682,-0.00490682,-0.00650676,-0.00490682,-0.00170694,-0.0081067,-0.00170694,-0.0081067,-0.00970664,-0.00650676,-0.00650676,-0.00330688,-0.00170694,-0.0081067,-0.00650676,-0.00490682,-0.00650676,-0.00490682,-0.00650676,-0.00650676,-0.0081067,-0.00330688,-0.00970664,-0.00650676,-0.00490682,-0.00650676,-0.00490682,-0.00330688,-0.00490682,-0.00330688,-0.00490682,-0.00650676,-0.000107004,-0.00490682,-0.00650676,-0.00650676,-0.0081067,-0.00490682,-0.00650676,-0.00650676,-0.00170694,-0.00490682,-0.00330688,-0.00490682,-0.00490682,-0.00330688,-0.0081067,-0.00490682,-0.00650676,-0.00330688,-0.00490682,-0.00490682,-0.00330688,-0.00330688,-0.00490682,-0.0081067,-0.00330688,-0.00330688,-0.00490682,-0.00490682,-0.0081067,-0.00170694,-0.00330688,-0.00490682,-0.00330688,-0.00490682,-0.00490682,-0.00650676,-0.00490682,-0.00490682,-0.00490682,-0.00490682,-0.00330688,-0.00650676,-0.00330688,-0.00490682,-0.00330688,-0.00330688,-0.00490682,-0.0081067,-0.00650676,-0.00650676,-0.0081067,-0.00970664,-0.00490682,-0.00650676,-0.00170694,-0.00170694,-0.00170694,-0.00650676,-0.00490682,-0.0081067,-0.00490682,-0.00170694,-0.00330688,-0.00650676,-0.00330688,-0.00650676,-0.00330688,-0.00490682,-0.00490682,-0.00650676,-0.00490682,-0.00970664,-0.00330688,-0.00650676,-0.00490682,-0.00650676,-0.00330688,-0.00490682,-0.00650676,-0.00650676,-0.00490682,-0.00650676,-0.00330688,-0.00170694,-0.00650676,-0.00330688,-0.00650676,-0.00490682,-0.00490682,-0.00490682,-0.00330688,-0.00330688,-0.00490682,-0.00490682,-0.00330688,-0.00650676,-0.00490682,-0.000107004,-0.0081067,-0.00650676,-0.00490682,-0.00650676,-0.00490682,-0.00330688,-0.00650676,-0.0081067,-0.00330688,-0.0081067,-0.00650676,-0.00490682,-0.00490682,-0.00490682,-0.00650676,0.00149293,-0.00490682,-0.00490682,-0.00650676,-0.00490682,-0.00170694,-0.00650676,-0.00650676,-0.00650676,-0.00490682,-0.00170694,-0.00330688,-0.00490682,-0.00170694,-0.00650676,-0.0081067,-0.00490682,-0.00330688,-0.00970664,-0.00970664,-0.000107004,-0.00650676,-0.00490682,-0.00330688,-0.00490682,-0.00650676,-0.00490682,-0.0081067,-0.0081067,-0.00650676,-0.0081067,-0.00650676,-0.00650676,-0.0081067,-0.00650676,-0.00490682,-0.0081067,-0.00490682,-0.0081067,-0.00970664,-0.00490682,-0.00490682,-0.00970664,-0.00650676,-0.00170694,-0.00650676,-0.00490682,-0.00650676,-0.00650676,-0.00170694,-0.00330688,-0.0081067
};
int i=0;
int count = 0;
int time_size = 502;
/*int amp_size = 6;
printf("FIRST Pre - Filtered Time = %e \n", time[0]);
double time [] -= float time[0];*/
printf("Non-Filtered TIME AND AMPLITUDE: \n");
Non: for(i = 0; i < time_size; i++){
printf("Non - Pre - Filtered Time = %e \t", time[i]);
printf("Non - Pre - Filtered Amp = %f \n", amp[i]);
count++;
}
printf("Pre-Filtered TIME AND AMPLITUDE: \n");
double time_2[502]={};
double amp_2[502]={};
for(i = 0; i < time_size; i++){
time_2[i]= time[i] - time[0];
amp_2[i] = -amp[i];
printf("Pre - Filtered Time = %e \t", time_2[i]);
printf("Pre - Filtered Amp = %f \n", amp_2[i]);

}

return 0;
}

Things We Should All Know (Petalinux)

The Xilinx tool-chain, as it pertains to running Petalinux on the Zedboard is as follows:

Vivado HLS --> Vivado  --> Petalinux --> SDCard (Boot on Board).

To fully  understand what is happening at each of these stages I will go through it step by step.

C) Developing Petalinux: an operating system to be installed on the Zedboard

PetaLinux is our full Linux distribution which includes the Linux OS as well as a complete configuration, build and deploy environment for Xilinx silicon. Because PetaLinux is fully featured, integrated, tested, and documented, it is the recommended and supported Linux deployment mechanism for our customers.

Steps

• Install Petalinux if it is not already installed:
• http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html
• In a terminal, navigate to the directory where you have saved both your Vivado HLS and Vivado Projects.
• Type the command:
• petalinux-create --type project --template zynq --name <Project Name>
• Where <Project Name> is the name of your project (e.g. Pre_Filter_petalinux)
• Change to project directory (the one you just created above e.g. Pre_Filter_petalinux)
• Type the command:
• petalinux-config --get-hw-description=<path-to-directory-which-contains-hardware-description-file>
• Note that the hardware description file is typically located in the .sdk/xxx_hw_platform_0 directory.  For example, on my system the directory is '/home/zynquser/Projects/working/HLS_Test/Pre_Filter/Pre_Filter.sdk/Pre_Filter_wrapper_hw_platform_0'     
• A GUI will appear, choose exit to exit and save the current settings.
• Enter the kernel configuration program and remove the auto internet configuration. There are problems with connecting the Ethernet cable to the Zedboard, so we remove this functionality
• Type the command:
• petalinux-config -c kernel
• deselect Networking Support --> Networking Options TCP/IP networking
• Save Settings and Exit GUI
• Ensure you are in the Petalinux project directory (e.g. Pre_Filter_petalinux):
• Type the command:
• petalinux-build
• wait a few minutes, this takes awhile
• To generate a boot image for the Zynq system:
• Type the command:
• petalinux-package --boot --fsbl <FSBL image> --fpga <FPGA bitstream> --u-boot --force
• Both files will be located in a directory similar to this:
• /home/zynquser/Projects/working/HLS_Test/Pre_Filter_peta/images/linux/zynq_fsbl.elf
• /home/zynquser/Projects/working/HLS_Test/Pre_Filter_peta/images/linux/Pre_Filter_wrapper.bit
• Copy the following files from /home/zynquser/Projects/working/HLS_Test/Pre_Filter_peta/images/linux/ to an SD card:
• Boot.BIN
• Image.ub
• Place the SD Card inside the Zedboard and turn on the board. Disconnect the Cypress UART cable from the Virtual Machine and connect it  to the Host Machine:
  
• Choose PuTTy from Windows Start Menu and choose the correct USB Serial Port (can be found in Device Manager in Control Panel)
• Press enter and you should see a boot sequence on the terminal
• Type in username and password:
• User: root
• PW: root

• 
  

Things We Should All Know (Vivado)

The Xilinx tool-chain, as it pertains to running Petalinux on the Zedboard is as follows:

Vivado HLS --> Vivado  --> Petalinux --> SDCard (Boot on Board).

To fully  understand what is happening at each of these stages I will go through it step by step.

B) Creating a Block Design in Vivado Design Suite

Vivado HLS automates  the construction of an IP core (block) that can be inserted into a hardware design (block diagram) to be eventually integrated with Petalinux.

Steps

• Open Vivado (on the command line, any directory, type: vivado)
• Create a new Project --> Pre_Filter as the name
• Follow the instructions from the Zynq Book Tutorial (part 1 to complete the initialization instructions including adding the processing system to your block design, link to download tutorials below, First Designs in Zynq is the header for where you should start)
• http://www.zynqbook.com/download-tuts.html
• Add 3 AXI GPIO Blocks, one for the LEDs, one for the push buttons, and one for the DIPs switches, and run connection automation
• Add HLS repository --> Choose Project Settings under Project Manager in Flow Navigator
• Choose IP on the left pane and click the "plus" icon to add a fresh IP repo
  
• The repository you want to add is in the HLS directory:
•  <you choose initial path>/Pre_Filter.prj/solution1/impl/ip
• Click Apply and OK
• In your block design window, select Add IP again. This time type "Pre" (or whatever your top function name was in HLS) and select the block that comes from the repository. It will look like this when it is added:

• Click on the processing system block in your design to open up Re-customize IP:
  

• Select IRQ_F2P[15:0] from PL-PS Interrupt Ports. Fabric Interrupts will need to be checked also (see above picture)
• Connect the interrupt port from the HLS IP block to the  IRQ_F2P[0:0] port of the processing system:

• Click Regenerate Layout, and your block design should look close to this: 

• Click Validate Design to ensure no design errors
• Create HDL wrapper inside the sources tab --> right -click yellow pyramid file, Create HDL wrapper:
  
• In the Flow Navigator, click Generate Bitstream. This command Runs Synthesis, Runs Implementation, and Generates the Bitstream (describing the programmable logic)
• This task will take a while, don't fret
• Click File --> Export Hardware
• Click File --> Launch SDK to update the old hardware design

You have now created a block design that uses a custom IP with interrupt connected to a Zynq processing system. The next step is to integrate the hardware description file (just created in Vivado) into Petalinux so that every module created in Vivado, whether its our module, the LEDs, the buttons, or the switches can be accessed on the Zedboard.

(see next blog) 

Things We Should All Know (Vivado HLS)

The Xilinx tool-chain, as it pertains to running Petalinux on the Zedboard is as follows:

Vivado HLS --> Vivado  --> Petalinux --> SDCard (Boot on Board).

To fully  understand what is happening at each of these stages I will go through it step by step.

A) Developing IP in Vivado High-Level Synthesis

Vivado HLS is a tool used to accelerate IP creation by enabling C/C++/SystemC programs (in our case I translated the first part of the PSD Python algorithm called Pre-Filter from Python to C, so it could be used in HLS and run on the Zedboard) to be directly targeted into Xilinx Programmable devices (Zedboard) without the need to manually create RTL.

Steps

• Open Vivado HLS (on the command line, any directory, type: vivado_hls)
• Create New Project --> Pre_Filter.prj --> Next
• Add Source Files --> Pre_Filter.c (can be found on another blog, but great to write your own) --> Next
• Top Function can be selected from browse (called Pre)
• The top function is the function that will be synthesized
• Add TestBench Files --> Pre_Filter.c --> Next
• Our test bench will be the same as our source file
• Choose Zedboard in Part Selection --> Finish
• Solution Name: High-Level Synthesis provides the initial default name solution1 but any name can be specified for the solution. 
• Clock: The clock period is specified using units of ns. The clock period used for synthesis is the clock period minus the clock uncertainty. High-Level Synthesis uses the timing information in the technology library to create the RTL design. The clock uncertainty value allows a user controllable margin to account for any increases in net delays due to RTL synthesis, place and route. If not specified in ns, the clock uncertainty defaults to 12.5% of the clock period.
• Run C-Simulation (Project Tab --> Run C - Simulation)
• Ensure no errors occur during compiling, you would not want to get through the block design without a working code. This would most likely be found during synthesis anyhow, but its good practice to run the simulation as a check. 
• Insert Directive in Top Function

• On the right side of the screen, there are two tabs, Outline and Directive. On the Explorer, under Source, be sure to select your Pre_Filter.c file and load it into the main window. Then select Directive on the right side of the screen.
• Right-click on Pre and insert directive, choosing interface and changing the mode to s_axilite
  
• Run C-Synthesis (Project Tab --> Run C - Synthesis)
• Solution Tab --> Export RTL --> OK
• Select IP Catalog and VHDL

You are now ready to import your newly created IP into Vivado and complete your block design! (See next blog)

Ubuntu with Linaro GUI Working

We have the linaro GUI downloaded on the SD Card and it is working with the ZedBoard.

To run Ubuntu on the ZedBoard make sure of the following:
-SD card is in the board
-MIO4 and MIO5 are HIGH (all other MIO's are LOW)
-JP2 and JP6 are shorted
-all other jumpers are untouched
-Monitor connected via HDMI port

Turn on the ZedBoard and connect to the GTKTerm terminal
-115200 baud rate, 8 bit, 1 stop bit, no parity, no flow control
-Port name is usually dev/ttyACM0 or dev/ttyACM1
 -After a few seconds, the blue LED should turn on and the connection process will begin
 
Once connected to the terminal, you should see
zed-boot>

Run the command: run sdboot_linaro

Give the board a few minutes to load the GUI

The link below is the svenblog link with the detailed instructions on getting Linaro on the SD card.
http://svenand.blogdrive.com/archive/199.html#.Vt9Cj0QRGlP

Talking to ZedBoard/Secure Digital (SD) Card mounting and un-mounting

Setting Jumpers

MI05 and MI04 must be set to High (1) as shown in ZedBoard image (Image 1)

Image 1

Voltage Supply Pin or GND is indicated by VADJ and either select 2V5 or 1V8 (seen in Image 2)

Image 2

Now SD Card and the ZedBoard

Opening SDK and connecting the ZedBoard to the terminal properly will prompt: zynq> 

The ZedBoard will be lighten up accordingly to what Image 3 shows. 

Image 3

Mounting the SD Card command:

zynq> mount /dev/mmcb1k0p1 /mnt

Un-mounting the SD Card command:

zynq> unmount  /mnt

The image below shows the mounting process from terminal in SDK (Image 4)

Image 4

Proper command to poweroff the ZedBoard from the terminal:

zynq> poweroff

Image 5 shows this process in the terminal below.

Image 5

OPEN SOURCE LINUX

OPEN SOURCE LINUX

Our Command: opt/Xilinx/SDK/2013.4/gnu/arm/lin/bin

Steps:

1. Need to fetch source codes and then fetch linux kernel

in the terminal: git clone git://github.com/Xilinx/linux-xlnx.git
1.75GB

2. Now U-Boot: git clone git://github.com/Xilinx/U-boot-xlnx.gir

3. Device Tree Gen: git clone git://github.com/Xilinx/device-tree.git

Note: Need to add GPU core on PL


Fall Semester 2015 ZedBoard Research