Now we are using MAX11205PMB1 Peripheral Module and the following two links are the datasheets:
http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf
http://datasheets.maximintegrated.com/en/ds/MAX11205PMB1.pdf
The second page of the second datasheet has the chart listed below which tells that we will only use pins 3 and 4.
PIN SIGNAL DESCRIPTION
1 N.C. Not connected
2 N.C. Not connected
3 MISO
Data-ready output/serial-data output.
This output serves a dual function.
In addition to the serial-data output
function, the MISO pin also indicates
that the data is ready when it is pulled
logic-low by the IC. Output data
changes on the falling edge of SCLK.
4 SCK
2-wire serial clock. The host must apply
an external clock signal to shift data
out from the IC.
5 GND Ground
6 VCC Power supply
Steps for completing the hardware part
1. Add GPIO > right click to make external
2. Double Click GPIO > customize to make all outputs
3. IP Configuration set GPIO Width to 8
4. Run Block Automation
5. Run Synthesis
6. Open Constraints Wizard > use page 3 and page 9 to link the pins
http://zedboard.org/sites/default/files/documentations/ZedBoard_RevD.2_Schematic_130516.pdf
Make sure under Configure tab > I/O Standard is LVCMOS33
7. Run Synthesis
8. Generate Bitstream and launch SDK
9. SDK may have to re-generate BSP sources (under system.mss)
10. Run the following code:
Using chapter two of this link (Page 7), we were able to load an .xise file in vivado.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug911-vivado-migration.pdf
Schematic Design Entry tool forum:
http://forums.xilinx.com/t5/Design-Entry/Schematic-Design-Entry-Tool-in-Vivado/td-p/278260
The entry at the bottom of the page may be a possible route to looking at the schematic diagram. We are in the process of downloading the program mentioned in this forum from this link:
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html
Maxim User guide:
http://pdfserv.maximintegrated.com/en/an/UG5483.pdf
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