Monday, June 1, 2015

Today June 1st "Running Synthesis after changing ports"

When editing the AXIGPIO in the block design always make sure to the recreate HDL Wrapper and then check the ports according to PMOD JA1.

Heres what they should look like:

PMOD             Site          Bitt
JA10                Y11          7
JA9                  AA11       6
JA8                  Y10          5
JA7                  AA9         4
JA4                  AB11       3
JA3                  AB10       2
JA2                  AB9         1
JA1                  AA8         0


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1 comment:

  1. mmccolgaJune 1, 2015 at 5:21 PM

    I think these are inverted. I posted a figure with correct mapping.

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